The present inventive concept relates to semiconductor devices, and more particularly, to semiconductor memory devices capable of pulling-up one of a local line pair using a pull-up circuit.
As is conventionally understood, contemporary semiconductor memory devices use a sense amplifier circuit to sense data stored in each memory cell of a constituent memory cell array. Such semiconductor memory devices use certain circuits and techniques for equalizing the sense amplifier circuit to improve a data sensing speed.
Contemporary semiconductor memory devices typically have the ability to operate in a so-called “burst mode” that enables high speed data access operations (e.g., read operations).
Data access operations (e.g., write and read operations) are accomplished using a number of input/output (I/O) lines extending into the memory cell array. Given the size of many contemporary memory cell arrays, the I/O lines are hierarchically configured as local I/O lines or global I/O lines. In particular, assuming a semiconductor memory device having a stacked bank structure, the word lines and local data I/O line pairs are typically arranged in parallel while the local data I/O line pairs and global data I/O line pairs are typically arranged perpendicularly to one another.
In conventional semiconductor memory devices, all of the data access paths between bit line sensing amplifier circuits and I/O sensing amplifier circuits are pre-charged to the full-level of a power voltage. Unfortunately, this approach tends to increase write/read cycle times, and data sensing errors may arise due to impedance and/or voltage mismatch(s) related to the sense amplifier circuits.